The present invention relates to apparatuses and methods for testing semiconductor devices. More particularly, the invention relates to a universal decoder test board for use in such apparatuses and methods.
New semiconductor device designs are commonly tested in order to ensure that they function properly with the circuitry of the hardware with which they are to be incorporated in a final product. Semiconductor device fabricators typically obtain test circuit boards for each new device design. These boards, referred to as "device under test" (DUT) boards, are designed to interface with testers specific to a particular hardware manufacturer. A conventional DUT board has three essential functions: (1) To provide an appropriate electronic interface with a particular semiconductor device package design; (2) to scramble the package's pins to corresponding channels of a tester apparatus for a particular manufacture's hardware platform; and (3) to provide an appropriate electronic interface to the tester.
FIG. 1A shows various components of a conventional device under test. A semiconductor device package 100 is provided for testing. Conventional device package types include pin grid arrays (PGAs), plastic board grid arrays (PBGAs), plastic quad flat packs (PQFPs), and flip chip plastic board grip arrays (FC-PBGAs). Such packaged designs are well-known to those of skill in the art. In addition to the variety of different package types available for semiconductor devices, the devices may also be manufactured with a variety of different pin counts. Each separate device design and pin count has separate configuration requirements for interfacing with a hardware platform, or its corresponding test board. Therefore, a separate conventional DUT board is required for the testing of each new semiconductor device design.
Semiconductor device package 100 removably interfaces with a conventional DUT board 110 with the assistance of a test socket 102, as indicated by double-headed arrow 101. The socket 102 provides an appropriate electrical coupling in a cavity 103 between the package 100 and the test board 110. The socket 102 is typically bonded through appropriate electrical contacts on a lower surface 104 to an upper surface 112 of the test board 110. The lower surface 114 of the conventional DUT board 110 is designed to interface with a tester (not shown) for a specific manufacturer's hardware platform. Semiconductor device packages 100 of the same type and pin count may be tested on the DUT board 110 by being successively removably (or "interchangeably") engaged within the package engaging cavity 103 of the socket 102.
FIG. 1B shows a top plan view of a conventional DUT test board 110. The test board 110 is typically divided into three regions, each of which provides a particular function. Region 116 is dedicated to coupling with a semiconductor device package to be tested. This region is typically occupied by a test socket, such as described above. Region 118 is dedicated to the circuitry required to scramble the pins of the package being tested to their corresponding tester channels. Region 120 provides the appropriate contacts to the tester for a particular hardware manufacturer's platform. Each hardware platform typically has its own distinct configuration for interfacing with a semiconductor package. It should be noted that the terms "upper", "lower", "top" and "bottom" are used in a relative sense in this application and may be reversed.
While this system provides an effective way to test new semiconductor device package designs, it has the disadvantage that each new package design must have a separate DUT board associated with each tester. Each DUT board is costly and time consuming to develop and construct.
Accordingly, apparatuses and methods which reduce the time and cost associated with the testing of new semiconductor device package designs would be desirable.